DVFS in Low-Leakage Technology

Considering DFVS again, there are (were?) two potential strategies (Aesop: Tortoise v Hare):

Aesop's Fable - Whose approach is better?

1. Compute quickly with halt(s), or
2. Compute more slowly and finish just in time.

To compute quickly and halt we need a higher frequency clock but consume the same number of active cycles.

So the work-rate product, af, unchanged, so no power difference ?

No. Running the same number of work cycles at a lower frequency requires a lower voltage and hence we save energy according to V^2.

But: current geometries only have a narrow operating voltage range

Too low -> too much leakage.

Too high -> tunnelling and wear and heat.

So today, we operate at around one volt always and the trade off is just between high and low leakage technology - a static fab-time decision.

There are further (unexaminable) prospects on the table, such as dynamic body bias ...