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High-Level Synthesis Survey

HLS removes instruction-fetch and decode entirely. Custom register lengths also commonly used.

»A Survey and Evaluation of FPGA High-Level Synthesis Tools, Nane et al, IEEE T-CAD December 2015|

Kiwi (Greaves/Singh) Scientific Accelerator: CSharp programs are implemented on FPGA for high-performance with low energy.

Input and Hardware Waveforms from a tiny Kiwi HLS example.

Mentor Catapult

Microsoft Catapult

Synopsys SynphonyC

Cadence -

Altera/Intel - OpenCL SDK and A++ and Spectra-Q

LegUP

Xilinx Vivado HLS

»Reconfigure I/O - HLS from Go

A large number of failed startups ...


47: (C) 2012-18, DJ Greaves, University of Cambridge, Computer Laboratory.