Logic synthesisers and HLS tools cannot synthesise into hardware the full set of constructs of a general programming language. There are inevitable problems with:
And it is not currently sensible to compile seldom-used code to the FPGA since conventional CPUs serve well. »A Survey and Evaluation of FPGA High-Level Synthesis Tools, Nane et al, IEEE T-CAD December 2015|
Generating good hardware requires global optimisation of the major resources (ALUs, Multipliers and Memory Ports) and hence automatic time/space folding.
An area-saving approach New techniques are needed that note that wiring is a dominant power consumer in today's ASICs
The major EDA companies, Synopsys, Cadance and Mentor all actively marketing HLS flows.
Altera (Intel) and Xilinx, the FPGA vendors, are now also promoting HLS tools.
Many people remain highly skeptical, but with FPGA in the cloud as a service in 2017 onwards, a whole new user community is garnered.
Synthesis from formal spec and so on: This is currently academic interest only ? Except for glue logic?
Success of formal verification means abundance of formal specs for protocols and interfaces: automatic glue synthesis seems highly-feasible.
|46: (C) 2012-18, DJ Greaves, University of Cambridge, Computer Laboratory.|