The Perhaps interface consists of a single cell transmit fifo and a single cell receive fifo. The fifos are a byte wide, and connect directly to the fabric. The cache controller selects between the two uses, on transmission a cache line request has priority. On reception the port controller route byte determines the destination - cells with the loopback bit set are delivered to the Perhaps interface.
Transmission is achieved by loading the entire cell, including the
fabric and port controller route bytes, into the Perhaps fifo then
issuing a PTX command to the cache controller. If the fifo contains
less than the required 54 bytes (2 route, 4 header
and 48 payload)
then the final byte in the fifo will be replicated into the end of the
cell. If the fifo contains more than 56 bytes then transmission will
not take place and an error flag is raised. Otherwise the fifo will
always be emptied and either the transmission complete or the
NACK flag will be raised. Under control of a mask these flags may
cause an interrupt through the 68901. There is currently a bug in
the transmit system an additional zero byte should be written to the
fifo following the last data byte. Also the clock line appears to be
noisy resulting in extra bytes being strobed into the fifo giving AF
errors. This should now be fixed, though problems have been seen with
fabric investigation cells. The fifo is byte wide, but a store multiple instruction may
be used to write bytes from successive CPU registers.
When a cell marked with the loopback bit set is received it is offered
to the Perhaps system. If the receive fifo is non-empty then the cell
will be NACKed, otherwise the header and data bytes are written into
the fifo. Once a cell has been received a flag is raised which may
cause an interrupt, this flag is cleared when the fifo goes empty.
Single reads must be done from the fifo, use of a load multiple
will probably fail.