Digital signal processors (DSPs) are widely used in embedded
applications. Often high performance is required which results in
some fairly wacky architectures to maximise parallelism. These tend
to be difficult to program efficiently and it is often difficult for a
compiler to generate optimal code. Consequently, there is a bias away
from increased parallelism so a few large and complex but fast
arithmetic units are preferable even when many small but slower ALUs
could yield better aggregate performance. This is to the detriment of
chip size and, thus, cost.
Dataflow processors provide the synchronisation primitives necessary to
support highly parallel computation. The synchronisation
overhead is too large of most conventional integer applications but it
appears work better for DSP applications where more complex
fixed-point and floating-point calculations dominate. Also, since DSPs are
typically processing streams of data, a data-driven programming
paradigm seems appropriate.
This project involves design and register-level simulation of a
Dataflow DSP in order to obtain performance measures.
I've supervised similar projects on processor design but not this
I'm willing to supervise this project.