Hi, I'm Peter Rugg, a postdoc in the architecture group. My research is in applying CHERI to the RISC-V architecture.
Courses I've supervised: Digital Electronics, Discrete Maths, Introduction to Architecture, Cybersecurity, Cryptography, Hoare Logic and Model Checking.
Part II Projects I've supervised: "Parallelising sequence alignment" (2019-20), "Dynamic Binary Translator from Arm to RISC-V" (2020-21).
Email: first.last@cl.cam.ac.uk