Verilog Hardware Description Language

PLEASE NOTE: THIS IS AN OLD PAGE AND MANY LINKS NO LONGER WORK
PLEASE NOTE: THIS IS AN OLD PAGE AND MANY LINKS NO LONGER WORK
PLEASE NOTE: THIS IS AN OLD PAGE AND MANY LINKS NO LONGER WORK

Research at Cambridge

• Comments on the twelve-page paper The Semantic Challenge of Verilog HDL will be gratefully received. This is a revised version of a paper to accompany an invited talk given at the Tenth Annual IEEE Symposium on Logic in Computer Science (LICS'95), June 26-29, 1995, San Diego, California.

• David Greaves and Mike Gordon have a Verilog-based research project entitled Checking Equivalence Between Synthesised Logic and Non-Synthesisable Behavioural Prototypes (also available as a postscript document) which is funded by the Engineering and Physical Sciences Research Council (EPSRC). Daryl Stewart is the Research Assistant on this project. Please let us know if you are interested in this work.

The Verilog-Archive page

• The Verilog-Archive page provided as a service to the Verilog community by Silicon Logic Engineering

Free Verilog simulators

• ViperFree: a free version of Viper, a commercially available Verilog simulator from InterHDL
• Veriwell: a free Verilog simulator from Wellspring Solutions

Syntax and semantics of Verilog

• Verilog simulation semantics
  (from IEEE 1364 Draft document: DRAFT STANDARD VERILOG HDL)
• Verilog Formal Syntax Specification
  (based on Language Reference Manual, Version 2.0)
• Draft semantics for use in the VFE project.

Companies

• Cadence
• Chronologic, which is currently in dispute with Viewlogic
• Verilog-MATLAB link by The Yokogawa Electric Corporation
• Silicon Sorcery
• Synopsys
• TriQuest
• Doulos who have a nice hardware designers guide to Verilog and their own Verilog FAQ
• Verification 97 seminars (Quickturn, SpeedSim, Chrysalis, Systems Science)

Books

• Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar
• A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog by Douglas J. Smith
• A Verilog HDL Primer by J Bhasker

Language wars

• VHDL's revenue is falling, but Verilog's is rising
• "COSTELLO SLAMS INTO VHDL"
• John Cooley's article on the Verilog/VHDL Wars
• Verilog Won & VHDL Lost? -- You Be The Judge!
• VHDL & Verilog Compared and Contrasted by Douglas J Smith (postscript)
• Verilog - accelerating digital design by Gerard M Blair (postscript)
• John Sanguinetti on why Verilog is beating VHDL

Miscellaneous

• Open Verilog International (OVI)
• Model Logic have an online Verilog course which includes a history of Verilog and a glossary.
• Bucknell Verilog Manual
• Gerard Blair's resources for Verilog for sychnronous digital design
• Official Verilog FAQ (temporarily unavailable), alternative Verilog FAQ and other useful stuff and VHDL FAQ
• VITAL (VHDL Initiative Towards ASIC Libraries)
• 1995 High-Level Synthesis Design Repository
• CAD resources
• VIUF Internet Services (VIIS) Server (vhdl.org)
• verilog2vhdl Verilog to VHDL translation
• DA-Related Information on the WEB from CADmazing Solutions
• WWW Site for DAC '95
• E2W3: Electrical Engineering on the World-Wide Web
• Electrical Engineering Circuits Archive
• Dagstuhl Seminar "CA Design and Test" (lots of BDD papers)
• Binary Moment Diagrams (Bryant/CMU)
• Don Thomas (author of The Verilog Hardware Description Language)
• Internet edition of Electronic Engineering Times
• Celia's Verilog & Synthesis Web Page
• Survey of design errors and problems they can cause
• Verilog coding guidelines, with synthesis issues in mind (by Synthesis Solutions)
• SIGDA Web Server
• Behavioral Synthesis Methodology for HDL-Based Specification and Validation: a paper by D. Knapp, T. Ly, D. MacMillen, R. Miller of Synopsys Inc
• Desktop Verilog for Synthesis: a downloadable course on synthesis with Verilog by Sylvan Technology

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