Costello gave a first person history of the EDA industry's technology, how it came about and how it was accepted at first. He detailed early hardware description languages working at the transistor level all the way through to high level synthesis. Then, with his usual flare for the dramatic, he paused and said: "VHDL is one of the biggest mistakes the Electronics Design Automation industry has ever made." -- which thrilled many a Verilog bigot in the room and caused the reporters to furiously scribble in their notebooks. (I'm told that this quote later had caused some grief in the mostly pro-VHDL European trade press with headlines like "COSTELLO SLAMS INTO VHDL.")
Joe's reasoning was that VHDL has forced all the EDA vendors & semiconductor foundries to double their EDA/CAD engineering staffs to support two completely different, but functionally equivalent, hardware description languages instead of one. (What Costello was lamenting was not VHDL per se, but the development of any second HDL that wasn't any more advanced than Verilog has been all along. It was just $400 million of duplicate effort for the EDA industry as a whole.) He concluded with: "Wouldn't this money have been better spent on handling submicron design, testability issues, or even a new type of HDL that had significantly more capabilities than what Verilog and VHDL offer today?"
What this speech told me was that Cadence was probably making a hell of a lot more money selling Verilog-XL than Leapfrog VHDL (because he risked alienating his VHDL customers with such misquoteable statements) and that Cadence was going to be eventually introducing a new hardware description language that he thinks will be leaps & bounds above either Verilog or VHDL (because he heavily hinted at this in his closing statements.) Now let's see how these May Day Parade watching predictions bear out...
[Extract from John Cooley's conference report in comp.cad.synthesis distributed by Jon.Saul@comlab.oxford.ac.uk via hwcomp@comlab.oxford.ac.uk]