Tutorial for the v0.4 lowRISC release
By Jonathan Kimmitt and Wei Song (Stefan Wallentowitz co-authored the previous version)
Release version 0.4 (04-2017)
Introduction
lowRISC is a not-for-profit organisation whose goal is to produce a fully open source System-on-Chip (SoC) in volume. We are building upon RISC-V processor core implementations from the RISC-V team at UC Berkeley. We will produce a SoC design to populate a low-cost community development board and to act as an ideal starting point for derivative open-source and commercial designs.
In previous tutorials you can learn about trace debugging, the initial tagged memory implementation or how to run the design on an FPGA using our original untethered implementation.
This tutorial adds further functionality towards the final SoC design:
- The addition of tag cache, with further optimisations vs our previous releases
- A tag pipeline to allow customised tag rules and for tags to be used to enforce program invariants
- A Minion core supporting commodity PC peripherals such as a 4-bit SD-card control, VGA-compatible display, and USB-keyboard - bare-metal and from Linux.
The previous debug infrastructure is still available but optional for the end-user. The build environment and pre-built images support the same platform as the previous releases, a low-end Nexys™4 DDR Artix-7 FPGA Board.