Jonathan Woodruff
Dr Jonathan Woodruff is a Senior Research Associate with expertise in processor architecture and microarchitecture as well as low-level software optimisation. Specialising in capability processor design, he has pushed into full-system optimisations including cache hierarchy, core timing, and multi-core designs as well as explorations into major security approaches including control flow integrity and private execution.
Publications
- Jonathan D Woodruff, CHERI: A RISC capability machine for practical memory safety , PhD thesis, University of Cambridge Technical Report 858, July 2014
- Jonathan Woodruff, Robert NM Watson, David Chisnall, Simon W Moore, Jonathan Anderson, Brooks Davis, Ben Laurie, Peter G Neumann, Robert Norton, Michael Roe, The CHERI capability model: Revisiting RISC in an age of risk, 41st International Symposium on Computer Architecture (ISCA), June 2014
- Robert NM Watson, Peter G Neumann, Jonathan Woodruff, Jonathan Anderson, David Chisnall, Brooks Davis, Ben Laurie, Simon W Moore, Steven J Murdoch, Michael Roe, Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture, University of Cambridge Technical Report 850, May 2014
- Robert NM Watson, David Chisnall, Brooks Davis, Wojciech Koszek, Simon W Moore, Steven J Murdoch, Jonathan Woodruff, Bluespec Extensible RISC Implementation (BERI): Software reference, University of Cambridge Technical Report 853, April 2014
- Robert NM Watson, Jonathan Woodruff, W Simon, Steven J Murdoch, Peter G Neumann, Robert Norton, Michael Roe, Bluespec Extensible RISC Implementation (BERI): Hardware reference, University of Cambridge Technical Report 852, April 2014
- Robert NM Watson, David Chisnall, Brooks Davis, Wojciech Koszek, Simon W Moore, Steven J Murdoch, Peter G Neumann, Jonathan Woodruff, Capability Hardware Enhanced RISC Instructions (CHERI): User's guide, University of Cambridge Technical Report 851, April 2014
- Jonathan Woodruff, A Theodore Markettos, Simon W Moore, A 64-bit MIPS processor running freebsd on a portable FPGA tablet, 23rd International Conference on Field Programmable Logic and Applications (FPL), September 2013
- Robert NM Watson, Peter G Neumann, Jonathan Woodruff, Jonathan Anderson, Ross Anderson, Nirav Dave, Ben Laurie, Simon W Moore, Steven J Murdoch, Philip Paeps, Michael Roe, Hassen Saidi, CHERI: a research platform deconflating hardware virtualization and protection, Workshop paper, Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE), March 2012
- A Deficit Round Robin Input Arbiter for NetFPGA, Master's thesis, Cambridge University Engineering Department, June 2010
- Jonathan Woodruff, Greg Chadwick, Simon Moore, Cache Tracker: A Key Component for Flexible Many-Core Simulation on FPGAs, WARP-5th Annual Workshop on Architectural Research Prototyping, June 2010
Contact Details
- Jonathan.Woodruff (at) cl.cam.ac.uk
- Room SC18, William Gates Building