ARM project (De1, 14)

Project leader: Frank Stajano
Demonstrators: Panit Watcharawitch, Tom Kelly

This project is based on the ECAD and Architecture workshops designed and lectured by Dr Simon Moore at the Computer Laboratory of the University of Cambridge. Simon's cooperation has been invaluable and is very gratefully acknowledged.

Introduction

This 4-week project sits at the boundary between hardware and software. You will be designing hardware circuits and programming a RISC processor. More specifically, you will build circuits by programming an Altera FPGA in Verilog (a hardware description language), and you will connect those circuits to an ARM 7 processor that you will program in ARM assembly language.

The goal of the project is to build a mouse interface for the ARM and write a rudimentary device driver allowing the ARM to read out the absolute 2D position of the mouse.

Deliverables

1. Electronic Die in Verilog
2. String sort in ARM assembler
3. Mouse interface in Verilog
4. Reading the mouse from the ARM

By the last session of every week you must produce a mini-report and give a live demonstration of your running hardware to one of the demonstrators. The mini-report is much shorter than the usual "interim reports" of most other projects and contains practically no prose. It consists of your commented ARM/Verilog code plus brief answers to a couple of questions on that week's task. You must give your demo and hand in your mini-report by the last timetabled session of each week (Thursdays 11:00-13:00). This is a serious deadline that nobody should miss: the penalty for late demos/mini-reports is 3 marks per weekday (Mon-Fri), which means you'd waste at least 6 marks since there is no session on Fri. It is of course acceptable and laudable to submit a mini-report ahead of time at some earlier session, although there are no bonus marks for this.

To submit a mini-report:

• Complete the Verilog code (and/or ARM code as appropriate) required for that week's subtask.
• Comment the code thoroughly and put answers to questions at the end of your code. Ensure that you add the subtask's title and your name to the top of the code. Print this out. This is your mini-report.
• Show a running demonstration of your work to a demonstrator to have it assessed, and hand in your mini-report to her or him at that time.

By 17:00 on Friday 7th June (last day of week 4, but not a timetabled session) you must hand in (to the Teaching Office) a final report of not more than 10 pages. See the bottom of the page for week 4 for advice on how to structure it. You will append copies of your 4 mini-reports to it. This is an even more serious deadline and no extension can be permitted.

Marking

Each mini-report is worth up to 15 marks, for a subtotal of 60 marks. The criteria that will be used for assessment are the following, of which the first will carry the most credit.

• Demonstrating a live working solution
• Clearly commenting and formatting the code
• Correctly answering the questions

A further 20 marks are awarded at the end of the project. The final report (worth up to 15 marks) will be assessed on the following criteria.

• Giving a logical and complete account of what was done
• Demonstrating a grasp of the core ideas and skills acquired during the project
• Clarity of ideas
• Clarity of language (readability and correctness of your English prose)

The remaining 5 marks will be awarded based on a live demonstration of a working solution for the whole project. Note that this is the same as the week 4 demo; you won't have to give it twice, it will just count more than the others in the final score.

The total for the whole project is therefore 80 marks.

Note that this is not a team project and all work must be carried out individually.

Bonus Track (new)

Given your feedback about the pace being a little slow, but given also the extremely wide variance in completion times for the week 1 task, I hereby introduce this optional bonus track for those of you who can complete the standard tasks in much less time than allocated, but find little incentive to carry out additional work unless it's marked. Note in passing that, if week 1 is any indication, completing a weekly task as soon as possible doesn't usually yield the highest marks. It is advisable to complete the 4 tasks of the standard track with elegance and style before devoting time to the bonus track.

The main deliverable for the bonus track is a ps2 keyboard interface, with interrupt-based (this is a requirement too) device driver, attached to the "string sort" program of week 2. The user must be able to enter the input strings on a keyboard attached to the Altera board, and these should be sorted and printed on the console of the ARM debugger.

Unlike with the standard tasks, there will be no handholding. You will have to find out about the ps2 keyboard protocol by yourself (web search, library search, reverse engineering, whatever) and all the design choices will be your own. See the bottom of ECAD workshop 6 for hints on interrupt-driven device drivers.

There are two auxiliary deliverables: implement the 2-second delay line mentioned at the bottom of the page for week 1, and the prime number program from ECAD workshop 4. You have to show these to a demonstrator, but you must not submit the corresponding code.

If you choose the bonus track, the rules for marking change as follows. Firstly, you must submit all 4 weekly mini-reports and show a running solution to the two auxiliary deliverables. Until you do this, your bonus track deliverable won't be looked at (let alone marked). Having done this, you must show a running solution for the main deliverable (the ps2 keyboard feeding the string sort program), write a report about it (max 2 sides of A4) and include the code as an appendix.

• The live demos of the auxiliary bonus deliverables attract no marks (but are required as preliminaries).
• The live demo of the main bonus deliverable gets the 5 marks normally allocated to the standard end-of-project demo (which you still have to do as part of the week 4 deliverable).
• The written report for the main bonus deliverable is worth up to 15 points and replaces, at your own risk if you submit it, the lowest-scoring of your first three mini-reports.
• Up to 5 bonus points (yes, for a total of 85/80, later clipped to 80) may be awarded for successful completion of the bonus track.

Timetable

This project runs in the Cockroft 4 teaching laboratory on the New Museums Site (follow the links for directions; this is NOT on the Engineering site).

Repeat the following pattern for 4 weeks, starting Monday 2002-05-13.

2h slot	Mon	Tue	Wed	Thu	Fri	Sat	Sun
09:00-11:00	Mandatory
11:00-13:00				Mandatory
13:00-15:00	Mandatory			NOT AVAILABLE
15:00-17:00	Mandatory			NOT AVAILABLE

"Mandatory" means it's a timetabled session for this project. You have to be there at those times or you will be penalized at the rate of 1 mark per hour missed. I will use about 4 of these 8 hours, depending on the week, to introduce you to Verilog and ARM assembler. You will use the rest to program the devices yourself. During these sessions you will each have access to an individual workstation with the appropriately licensed software tools, and you will be issued one teaching board each. Demonstrators will be available to provide guidance and to help you using the tools.

"NOT AVAILABLE" means the room is booked for another course, so you can't be there at those times.

All the other slots are currently free, so you are welcome to go there and use the available facilities when it best suits you. At those unsupervised times, however, only 9 workstations will be equipped with teaching boards; the others will have just the software tools.

Remember that your work for each week is assessed by a demonstrator on the Thursday of that week, so you have no extra time to clean things up afterwards or at the weekend.

Departmental warnings

• For non-attendance at timetabled sessions you will lose 1 mark per hour missed.
• For late submission of interim reports you will lose 3 marks per weekday.
• No extension to the final report deadline of 17:00 on Friday 7 June will be permitted.
• You will have to sign a declaration that you are submitting your own work.
• You will not receive any indication of any marks for your interim or final reports. Your college may inform you of your final mark after publication of the final class lists.
• Any applications for allowances for illness must be submitted by your College Tutor to the Teaching Office as soon as possible, and not later than Monday 10 June.

Useful online references

All in HTML except where marked.

Verilog

• Dan Hyde's Verilog handbook (also available as PDF) is a fairly complete description of the language.
• Tutorial slides (PDF) by Donald Thomas, co-inventor of Verilog.
• The Doulos tutorial on Verilog.
• Optimagic has a small link farm of VHDL references and tutorials.

ARM assembler

• Peter Cockerell's excellent 1987 book ARM Assembly Language Programming (HTML and PDF) is a useful reference to keep around while writing code, particularly chapter 3, The Instruction Set.
• Concise summaries can also be found in Simon Moore's Computer Design (PDF) course notes, in lectures 3 and 4.
• I can't put a link to it from here, but the ARM developer suite comes with a library of "Online books" about the tools and the ARM processor itself. You can access this documentation from the Start menu: the shortcut is in the same menu from which you launch Code Warrior.

ARM/Altera teaching board

• The home page and FAQ for Simon Moore's ECAD and Architecture workshops at the Computer Laboratory on which this project is based.
• Documentation for the board, from an extensive list of memos about the Altera/ARM hardware.

Related lecture course material

• Richard Prager's lecture notes on Combinational Logic (PDF), Sequential Logic (PDF) and Microprocessors (PDF).
• Simon Moore's lecture notes on ECAD (PDF) and Computer Design (PDF). Note that, by explicit request of the author, these files should not be accessed from outside cam.ac.uk, so please don't pass them on.
• The old lecture notes of David Greaves (who originally introduced me to Verilog and ARM assembler with a lively and instructive course) are still available at the Computer Lab in postscript. I have converted them to PDF, but owing to bitmapped fonts in the originals the results are not very good on screen (they print ok though). The most relevant to this course are the Verilog learner's guide, Verilog syntax charts 1 and 2, Debouncing handout, ECAD and Structured Hardware Design.