D J Greaves: Very High Level Simulation (and Modelling) TLM-POWER.
PAGE UNDER CONSTRUCTION.
Comparing TLM POWER 2 with Prazor:
TLM POWER 2:
- Deals with power 'modes' and 'phases' of subsystems
- Might be difficult to integrate with loosely-timed modelling ?
- Difficult to record energy consuming events, such as individual bus transactions,
- Power consumption for a component read from a table that must always be manually created.
Experimental Prazor (TLM POWER 3) System:
- Supports power and energy equally well, with power calculations being accurate at the end of each LT quantum.
- Requires each component to inherit the prazor base class (current implementation),
- Enables physical size of components to be logged (e.g. as a basis for nominal place and route),
- Allocates X-Y co-ordinates to each component,
- Wiring distances can be estimated using Rent's rule OR measured from X-Y coordinates if placed,
- Power/energy consumption for a component can depend on constructor args (e.g. memory size, bus width).
- Bit-level toggle counts within generic payloads optionally supported.
- No API for dynamic voltage scaling, but dynamic-frequency is kind-of intrinsic to the energy-logging approach.
A TLM Wrapper for the University of Maryland DRAMSIM2 simulator may be downloaded from the same place DRAMSIM2 TLM Wrapper Download (available already).
- 2012. `TLM POWER3: Power Estimation Methodology for SystemC TLM 2.0' DJ Greaves & MM Yasin. At FDL'12 Forum on specification & Design Languages. Vienna. September 2012. 6 pages. We report on a SystemC add-on library which extends every SystemC module with non-functional data regarding power consumption and physical layout and which accumulates and estimates dynamic energy usage. It supports both phase/mode power modelling and energy-per-transaction logging for TLM (transactional-level modelling). Wiring energy is computed by counting bit-level activity within the TLM generic payload. Each leaf component can also register its physical dimensions to facilitate a wire length estimator that traverses the SystemC model hierarchy using either full placement or Rent's rule estimators. It also supports dynamic voltage islands and inter-chip wiring, where each transaction can consume energy according to the current supply voltage of the relevant islands and the nature of the interconnect. We report on basic peformance from some SPLASH-2 benchmarks running on a modelled OpenRISC quad-core platform. Paper: Full Text PDF. Slides: SLIDES PDF.