Technical reports
Multithreaded processor design
February 1995, 125 pages
This report was also published as a book of the same title (Kluwer/Springer-Verlag, 1996, ISBN 0-7923-9718-5).
This technical report is based on a dissertation submitted October 1994 by the author for the degree of Doctor of Philosophy to the University of Cambridge, Trinity Hall.
| DOI | https://doi.org/10.48456/tr-358 |
Abstract
Multithreaded processors aim to improve upon both control-flow and data-flow processor models by forming some amalgam of the two. They combine sequential behaviour from the control-flow model with concurrent aspects from data-flow design.
Some multithreaded processor designs have added just a little concurrency to control-flow or limited sequential execution to data-flow. This thesis demonstrates that more significant benefits may be obtained by a more radical amalgamation of the two models. A data-driven microthread model is proposed where a microthread is a short control flow code sequence. To demonstrate the efficiency of this model, a suitable multithreaded processor called Anaconda is designed and evaluated.
Anaconda incorporates a scalable temporally predictable memory tree structure with distributed virtual address translation and memory protection. A temporally predictable cached direct-mapped matching store is provided to synchronise data to microthreads. Code is prefetched into an instruction cache before execution commences. Earliest-deadline-first or fixed-priority scheduling is supported via a novel hardware priority queue. Control-flow execution is performed by a modified Alpha 21064 styled pipeline which assists comparison with commerical processors.
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BibTeX record
@TechReport{UCAM-CL-TR-358,
author = {Moore, Simon William},
title = {{Multithreaded processor design}},
year = 1995,
month = feb,
url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-358.pdf},
institution = {University of Cambridge, Computer Laboratory},
doi = {10.48456/tr-358},
number = {UCAM-CL-TR-358}
}