Technical reports

A formalisation of the VHDL simulation cycle

John P. Van Tassel

March 1992, 24 pages

DOI: 10.48456/tr-249

Abstract

The VHSIC Hardware Description Language (VHDL) has been gaining wide acceptance as a unifying HDL. It is, however, still a language in which the only way of validating a design is by careful simulation. With the aim of better understanding VHDL’s particular simulation process and eventually reasoning about it, we have developed a formalisation of VHDL’s simulation cycle for a subset of the language. It has also been possible to embed our semantics in the Cambridge Higher-Order Logic (HOL) system and derive interesting properties about specific VHDL programs.

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BibTeX record

@TechReport{UCAM-CL-TR-249,
  author =	 {Van Tassel, John P.},
  title = 	 {{A formalisation of the VHDL simulation cycle}},
  year = 	 1992,
  month = 	 mar,
  url = 	 {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-249.pdf},
  institution =  {University of Cambridge, Computer Laboratory},
  doi = 	 {10.48456/tr-249},
  number = 	 {UCAM-CL-TR-249}
}