Technical reports

Formal validation of an integrated circuit design style

I.S. Dhingra

August 1987, 29 pages

DOI: 10.48456/tr-115

Abstract

In dynamic circuit design many rules must be followed which govern the correctness of the design. In this paper a dynamic CMOS design style using a two phase non-overlapping clock with its intricate design rules is presented together with formal means of showing that a circuit follows these rules.

Full text

PDF (1.2 MB)

BibTeX record

@TechReport{UCAM-CL-TR-115,
  author =	 {Dhingra, I.S.},
  title = 	 {{Formal validation of an integrated circuit design style}},
  year = 	 1987,
  month = 	 aug,
  url = 	 {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-115.pdf},
  institution =  {University of Cambridge, Computer Laboratory},
  doi = 	 {10.48456/tr-115},
  number = 	 {UCAM-CL-TR-115}
}