Technical reports

Hardware verification of VLSI regular structures

Jeffrey Joyce

July 1987, 20 pages

DOI: 10.48456/tr-109

Abstract

Many examples of hardware specification focus on hierarchical specification as a means of controlling structural complexity in design. Another method is the use of iteration. This paper, however, presents a third method, namely the mapping of irregular combinational functions to regular structures.

Regular structures often result in solutions which are economical in terms of area and design time. The automatic generation of a regular structure such as a ROM or PLA from a functional specification usually accommodates minor changes to the functional specification.

The mapping of irregular combinational functions to a regular structure separates function from circuit design. This paper shows how this separation can be exploited to derive a behavioural specification of a regular structure parameterized by the functional specification.

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BibTeX record

@TechReport{UCAM-CL-TR-109,
  author =	 {Joyce, Jeffrey},
  title = 	 {{Hardware verification of VLSI regular structures}},
  year = 	 1987,
  month = 	 jul,
  url = 	 {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-109.pdf},
  institution =  {University of Cambridge, Computer Laboratory},
  doi = 	 {10.48456/tr-109},
  number = 	 {UCAM-CL-TR-109}
}