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Computer Laboratory > Course material 2005-06 > ECAD


Principal lecturer: Dr Simon Moore
Taken by: Part IB

Past exam questions are in several places: [ECAD] [ECADTopics]


This year ECAD is being taught through an Interactive Verilog Compiler web system and four lectures.

Intelligent Verilog Compiler

The Intelligent Verilog Compiler (IVC) will be used for the first two laboratory sessions and completed as homework. The material the IVC covers is a prerequisite for the remaining seven practical sessions.

Start IVC

Lecture Handouts

The lecture notes are handed out at the first lecture. Further copies should be available from Student Admin. ( A PDF is also available from the domain only.

Related workshops

Please see ECAD and Architecture Practical Classes.


Lecutre 4, slide 15, module debounce2 would be better written as the following. There may also be an issue with Quartus synthesising the old version correctly.

module debounce2(clean_pb, pb, clk);
  output  clean_pb;
  input   pb,clk;

  parameter counter_bits=15;

  reg [counter_bits:0] count;
  reg [3:0] pb_history;
  reg clean_pb;

  always @(posedge clk) begin
    pb_history <= {pb_history[2:0],pb};

      count <= 0;
    else if(count[counter_bits])
      clean_pb <= pb_history[3];
      count <= count + 1;

Related external links

Examination information

There is one ECAD question in the Part Ib Tripos.