Computer Design

Aims

The aims of this course are to introduce the hardware/software interface models and the hardware structures used in designing computers. The first eight lectures are concerned with the hardware/software interface and cover the programmer's model of the computer. The last eight lectures look at hardware implementation issues at a register transfer level

Structure

This is a 16 lecture course lectured by Simon Moore. The course is split into two parts.

Part I - The Hardware/Software Interface

The first part of this course covers the programmer's model of the computer.

Lectures:

• 1 - introduction to the course and some background history
• 2 - historic machines: EDSAC vs Manchester Mark I
• 3 - introduction to RISC processor design and the ARM instruction set
• 4 - ARM tools and code examples
• 5 - operating system support + memory hierarchy & management
• 6 - Intel x86 instruction set
• 7 - Intel code examples
• 8 - Java Virtual Machine

Part II - Hardware Structures

The second part of this course looks at hardware implementation issues at a register transfer level.

Lectures:

• 9 - executing instructions - an algorithmic viewpoint
• 10 - basic processor hardware: pipelining & data paths
• 11 - extending the ARM pipeline - including load and branch delay slots
• 12 - memory hierarchy (caching, etc.)
• 13 - buses (internal communication pathways)
• 14 - communication interfaces and devices
• 15 - control structures (state machines and microcode)
• 16 - data-flow & comments on future directions

Recommended books

• Hennessy, J.L. & Patterson, D.A. (1996). Computer Architecture: A Quantitative Approach. Morgan Kaufmann (2nd ed.)
• Patterson, D.A. & Hennessy, J.L. (1998). Computer Organization and Design. Morgan Kaufmann (2nd ed.).

• Copies of the handouts will be made available at the first lecture and subsequently from Jenni Cartwright, our Student Administrator. Please note that the handouts only give an outline of the course. Annotations and additional examples are given in the lectures.
• Architecure workshops for Part 1B students (not taken by Diploma students)
• Example divide code for lecture 4
• Additional information for lecture 8
• Java version of the Booths algorithm for lecture 9

There are three tickable exercises (ECAD workshops 5, 6 and 7) taken by Part 1Bs only. There are hree Tripos questions for Part 1Bs and Diplomas.

Past exam questions:

• recent Computer Design questions
• older questions from the Processor Architecture Course which are still mostly relevant
• other example questions (in PDF format)

• Make a formal comment on the course or
• E-mail an informal comment to the lecturer: Simon.Moore at the lab

• a breif introduction to the ARM tools is presented in workshop 5
• EDSAC simulators
• online manuals and AEB user guide provided by ARM
• further information on using ARMs in embedded systems
• the GNU C compiler can be built as a cross compiler (e.g. compile ARM code on an Intel Linux box) - see gcc sources and the CrossGCC FAQ. If you're interested in this, then ARM Linux might also interest you.
• Intel architecture manuals
• Java VM Specification
• CPU Info Center including a table of benchmarks based on SPEC-marks
• Virtual museum of computing
• The Amulet project (self-timed ARM research)

Simon Moore