Principal lecturer: Dr Simon Moore
Taken by: Part IB, Part II (General), Diploma
Number of lectures: 16
Lecture location: Arts School Room A
Lecture times: 10:00 on TTS starting 27-Oct-98
This is a 16 lecture course lectured by Simon Moore.
The course is split into two parts.
Part I - The Hardware/Software Interface
The first part of this course covers the programmer's model of the
- 1 - introduction to the course and some background history
- 2 - historic machines: EDSAC vs Manchester Mark I
- 3 - introduction to RISC processor design and the ARM instruction set
- 4 - ARM tools and code examples
- 5 - operating system support + memory hierarchy & management
- 6 - Intel x86 instruction set
- 7 - Intel code examples
- 8 - Java Virtual Machine
Part II - The Hardware
The second part of this course looks at hardware implementation issues
at a register transfer level.
- 9 - executing instructions - an algorithmic viewpoint
- 10 - basic processor hardware: pipelining & data paths
- 11 - extending the ARM pipeline - including load and branch delay slots
- 12 - memory hierarchy (caching, etc.)
- 13 - buses (internal communication pathways)
- 14 - communication interfaces and devices
- 15 - control structures (state machines and microcode)
- 16 - data-flow & comments on future directions
- The handouts only give an outline of the course.
Annotations and additional examples are given in the lectures.
- Copies of the handouts will be made available at the first lecture
and subsequently from Jenni Cartwright, our Student Administrator.
IB | II(G) | Dip
Provisional information only
Generated at 09:55.16 on 4/9/1998