RTL Power Estimation by Static Analysis (ie Without Simulation)

Post RTL synthesis we have a netlist and can use Rent for wire lengths provided sufficient hierarchy exists (perhaps five or more levels). We can either use the natural hierarchy of the RTL input design or we can apply a clustering/clique finding algorithms to determine a rough placement floorplan without doing a full place and route.

Pre RTL synthesis we can readily collect the following certainties (and hence the static power (ignoring drive strength selection))

• Number of flip-flops
• Number and bit widths of arithmetic operators
• Size of RAMs

    module CTR16( 
      input mainclk, 
      input din, input cen,
      output o); 
 
      reg [3:0] count, oldcount; // D-types
 
      always @(posedge mainclk) begin
          if (cen) count <= count + 1;    // ALU
          if (din) oldcount <= count; // Wiring
          end

     assign o = count[3] ^ count[1]; // Combinational

   endmodule

But the following dynamic quantities require heuristic estimates:

• Flip-flop activity (number of enabled cycles/number of flipping bits)
• Number of writes to RAMs
• Glitch energy in combinational logic.