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NEXT (Illustrative, very simple SoC Bus.)
A SoC consists of interconnected IP Blocks
We
tour a number of IP (intellectual property) blocks. All will be targets, most will also generate interrupts and some will also be initiators.
Interupts will be conveyed by custom point-to-point nets. Data will use a 'bus'.
A bus conveyes a transaction from an initiating IP block on a target block and a response back again.
A transaction contains a command that typically selects one of the these forms:
- Single Word Write: as generated by a CPU store instruction,
- Single Word Read: ditto for CPU load,
- Burst Reads or Writes: as cache lines are loaded or evicted or for block moves (e.g. Ethernet datagram DMA),
- Laned Writes: byte stores mean that only certain parts of a word are dirty,
- I/O Read or Write: programmed input/output requires cache bypass,
- Load-locked: (aka load-linked) takes a lock on a memory location,
- Store-conditional: (aka store-exclusive) performs a write if lock not lost in the meantime,
- Memory Fence: (aka barrier) preserves RaW and WaW ordering,
- Evict or Snoop: for inter-cache consistency updates (e.g. ARM ACE protocol)
- (Misc Others: Presence probe, debug access, read-ahead warm up ...)
In complex SoCs, burst transactions are often conveyed as packets over a network-on-chip (NoC). Such a packet may be broken up into
»flits