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Illustrative, very simple SoC Bus.

In another section of these notes, we shall look at real-world busses like AXI, but we'll start simple here.

We do not use bi-directional (tri-state) busses within our SoC: instead our 'bus' consists of dedicated nets and multiplexor trees.

In this section we use the following RTL net names:

On an initiator the net directions will be reversed.

For simplicity, in this section, we assume a synchronous bus with no acknowledgement signal, meaning that every addressed target must respond in one clock cycle with no exceptions. Hence a cycle acknowledge handshake signal is not needed.

Also we assume only complete words are ever stored, so no byte lane qualifiers for bytes and halfwords are shown.


21: (C) 2008-17, DJ Greaves, University of Cambridge, Computer Laboratory.