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Part II CST SoC D/M Slide Pack 4 (RTL)
Verilog RTL: Modules, Protocols and Interfaces
Protocol and Interface
Transactional Handshaking
Transactional Handshaking in RTL (Synchronous Example)
RTL: Register Transfer Language
RTL Summary View of Variant Forms.
Structural Verilog
Generative Forms
Structure Flattening
2a/3: Continuous Assignment.
2b/3: Pure RTL : unordered synchronous register transfers.
3/3: Behavioural RTL
Comprehensive Illustrative Examples
Simulation And Synthesis.
Synthesisable RTL
Synthesis Example
Verilog RTL Synthesis Algorithm: 3-Step Recipe
Behavioural - `Non-Synthesisable' RTL
Further Synthesis Issues
Conventional RTL Compared with Software
Conventional RTL Conclusion
Alternatives to RTL
Logic Synthesis from Guarded Atomic Actions (Bluespec)
Simulation
Digital Logic Modelling
Event Driven Simulation
Inertial and Transport Delay
Compute/Commit Cycle With Delta Cycles
Higher-level Simulation
Static Timing Analyser Tool
Hazards
Example: Sequential Long Multiplication
Hazards From Array Memories
Overcoming Structural Hazards using Holding Registers
Folding, Retiming & Recoding
Critical Path Timing Delay
Back Annotation and Timing Closure
FIFOs
End of Pack