Synthesisable RTL (SRTL) looks a lot like software at first glance, but we soon see many differences.
SRTL is statically allocated and defines a finite-state machine.
Threads do not leave their starting context and all communication is through shared variables that denote wires.
There are no thread synchronisation primitives, except to wait on a clock edge.
Each variable must be updated by at most one thread.
Software on the other hand uses far fewer threads: just where needed. The threads may pass from one module to another and thread blocking is used for flow control of the data.
SRTL requires the programmer to think in a massively-parallel way and leaves no freedom for the execution platform to reschedule the design.
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