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High-Level Synthesis

Traditional RTL design entry (Verilog/VHDL) needs:

Performing a Time for Space re-folding (i.e. doing the same job with more/less silicon over less/more time) requires a complete redesign at this level!

Optimising schedules in terms of memory port and ALU uses ? Pen and paper?

Can we do better ? Want to use High-Level Synthesis.

Dark silicon facilitates 'Conservation Cores'. A paper at ASPOLOS'10 about putting common kernels in silicon and 'Reducing the Energy of Mature Computations' by power gating.

4: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.