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NEXT (Kiwi : Compiling Concurrent Programs to Hardware)
Semantics of a programming language when used for hardware description.
In Verilog, the rule for mapping the thread to hardware is simply
to update the real flip-flops with the values found in the
simulation time registers when the thread encounters the clock
event control statement (` \@(posedge clk)'). In languages
such as C and Java, there are no such clock statements.
There are no widely-accepted rules for converting C and Java to
hardware, but two suitable rules for functions and processes
can be summarised as:
- Combinatorial logic from functions: If a function
makes no use of global, free or static variables and the
number of times any loops in its body are executed can be
determined (easily) at compile time, then we can generate
a combinatorial circuit (network of gates) that does the
same thing.
- Infinite process loops: If the program contains a ` while
(1)' type header to a loop, then this will inevitably have input and
output operations in the body of the loop and the whole loop can
usefully be converted to a logic block which performs the same
function. The number of clock cycles that the logic block consumes
to loop the loop can be chosen by the compiler: it may vary on input
data. Also, the nature of the input and output statements supported needs to be defined: calls
to print functions are not likely to be intended for conversion to
hardware. Instead, inputs and outputs are likely to be reads and
writes to channels or static shared variables that map to standard
registers and RAM blocks in the hardware implementation.