Logic synthesisers and HLS tools cannot synthesise into hardware the full set of constructs of a general programming language. There are inevitable problems with:
Generating good hardware requires global optimisation of the major resources (ALUs, Multipliers and Memory Ports) and hence automatic time/space folding.
New techniques are needed that note that wiring is a dominant power consumer in today's ASICs
|28: (C) 2008-13, DJ Greaves, University of Cambridge, Computer Laboratory.|