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Classical High-Level Synthesis

Take one thread and a body of code:

generate a custom datapath containing registers, RAMs and ALUs
and a custom sequencer that implements an efficient, static schedule

that achieves the same behaviour.

Works well when there is little or no cycle time variation. Not so good with DRAM+cache or floating point.

Creates a precise schedule of addresses on register file and RAM ports and ALU function codes.

Typically unwinds inner loops by some factor.

Can cope with data-dependent control flow, but predicate hoisting needed if datapath is heavily pipelined.

Data-dependent control flow and RAM bandwidth ultimately limit parallelism.

Profiling or datapath description hints are needed for a sensible datapath structure since sequencer states are not equiprobable and we do not want to deploy resource on seldom-used data paths.