RAM Macrocell Compiler Tool

The average SoC is 71 percent RAM memory. The RAMs are typically generated by a RAM compiler. The input parameters are:

• Size: Word Length and Number of Words.
• Port description: Each port has an address input and is one of r, w, r/w.
• Clocking info: Frequency, latency, or access time for asynchronous RAM.
• Resolution: What to do on write/write and write/read conflicts.

The outputs are a datasheet for the RAM, high and low detail simulation models and something that turns into actual polygons in the fabrication masks.

  // Example low-level model for a RAM
  module R1W1RAM(din, waddr, clk, wen, raddr, dout);
    input clk, wen;
    input [14:0] waddr, raddr;
    input [31:0] din;
    output [31:0] dout; 

    reg [31:0] myram [32767:0];  // 32K words of 32 bits each.
    always @(posedge clk) begin
         dout <= myram[raddr];
         if (wen) myram[waddr] <= din;
         end

  // Example high-level model for a RAM
  SC_MODULE R1W1RAM()
  {
     uint32_t myram [32768];
     int readme(int A) { return myram[A]; }
     writeme(int A, int D) { myram[A] = D; }
  }

Sometimes self test modules are also generated. For example Mentor's MBIST Architect(TM) generates an SRTL BIST with the memory and ARM/Artisan's Generator will generate a wrapper that implements self repair of the RAM by diverting access from a fault row to a spare row. »ARM Artisan

Other related generator tools can be provided: e.g. a FIFO generator would be similar and a masked ROM generator or PLA generator.