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Static Timing Analyser Tool

Starting with some reference point, taken as D=0, such as the master clock input to a clock domain, we compute the relative delay on the output of each gate and flop.

For a combinational gate, the output delay is the gate's propagation time plus the maximum of its input delays.

For an edge-triggered flop, such as a D-type or a JK, there is no event path to the output from the D or JK inputs, so it is just the clock delay plus the flop's clock-to-Q delay.

There are event paths from asynchronous flop inputs however, such as preset, reset or transparent latch inputs.

Propagation delays may not be the same for all inputs to a given output and for all directions of transition. For instance, on deassert of asynchronous preset to a flop there is no event path. Therefore, may typically keep separate track of high-to-low and low-to-high delays.

(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.