Clock trees consume quite a lot of the power in an ASIC and considerable savings can be made by turning off the clocks to small regions. A region of logic is idle if all of the flip-flops are being loaded with their current contents, either through synchronous clock enables or just through the nature of the design.
Instead of using synchronous clock enables, current design practice is to use a clock gating insertion tool that gates the clock instead.
Care must be taken not to generate glitches on the clock as it is gated and transparent latches in the clock enable signal can re-time it to prevent this.
How to generate clock enable conditions ? One can have software control (additional control register flags) or automatically detect. Automatic tools compute `clock needed' conditions. A clock is `needed' if any register will change on a clock edge.
A lot of clock needed computation can get expensive, resulting in no net saving, but it can be effective if computed once at head of a pipeline.
Beyond just turning off the clock or power to certain regions, in LG8 we look at further power saving techniques: dynamic frequency and voltage scaling.