RAMs vary in their size and number of ports.
The 'hren' signal is not shown since the RAM is reading at all times when it is not reading.
Most RAMs in use on SoCs are synchronous with the data that is output being addressed the clock cycle before.
Most of today's SoC designs have more than fifty percent of their silicon area devoted to RAM.
RAMs below a few hundred bits should typically be implemented as register files made of flip-flops. RAMs require special test logic.
Commonly, synchronous RAMs are used, requiring one clock cycle to read at any address. The same address can be written with fresh data during the same clock cycle, if desired.
RAMs for SoCs are normally supplied by companies such as Virage and Artizan. A 'ram compiler' tool is used for each RAM in the SoC. It reads in the user's size, shape, access time and port definitions and creates a suite of models.
High-density RAM (e.g. for L2 caches) may clock at half the main system clock rate and may need error correction logic to meet the system-wide reliability goal.