HOME       UP       PREV       NEXT (RAM - on chip memory (Static RAM).)  

General Interrupt Structure

Nearly all devices have a master interrupt enable control flag that can be set and cleared by under programmed I/O by the controlling processor. Its output is just ANDed with the local interrupt source.

The programmed I/O uses the write enable (wen) signal to guard the transfer of data from the main data bus into the control register. A ren signal is used for reading.

The principal of programming is

With only a single interrupt wire to the processor, all interrupt sources share it and the processor must poll around on each interrupt to find the device that needs attention.

Enchancement: a vectored interrupt makes the processor branch to a device-specific location.

Interrupts can also be associated with priorities, so that interrupts of a higher level than currently being run preempt.


(C) 2008-10, DJ Greaves, University of Cambridge, Computer Laboratory.