Hands-on with the NetFPGA
to build a Gigabit-rate Router
Andrew W. Moore,
Martin Zadnik, and David Miller
Tuesday, September 16th and Wednesday September 17th, 2008
9am - 5pm
Registration is now closed - the course is full.
(Old) Registration details here
University of Cambridge,
Room FW11, 1st Floor,
William Gates Building,
15 JJ Thomson Ave, CB3 0FD, UK
An open platform called the NetFPGA
has been developed at Stanford University.
The NetFPGA platform enables researchers and instructors to
build high-speed, hardware-accelerated networking systems.
The platform can be used in the classroom to teach students how to build
Ethernet switches and Internet Protocol (IP) routers using hardware
rather than software. The platform can be used by researchers to prototype
advanced services for next-generation networks.
By using Field Programmable Gate Arrays (FPGAs),
the NetFPGA enables new types of packet routing circuits to be
implemented and detailed measurements of network traffic to be obtained.
During the tutorial, we will use the NetFPGA to determine
the amount of memory needed to buffer TCP/IP data streaming through
the Gigabit/second router.
Hardware circuits within the NetFPGA will be implemented
to measure and plot the occupancy of buffers.
Circuits will be downloaded into reconfigurable hardware and tested with live,
streaming Internet video traffic.
Attendees will utilise a Linux-based PC equipped with NetFPGA hardware.
A basic understanding of Ethernet switching and network routing is expected.
Past experience with Verilog is useful but not required.
This first day of this full-day tutorial emulates previous the successful one-day held at Hot Interconnects 2007
and builds upon the Eurosys 2008 tutorial held earlier this year.
from that event as well as the handouts
are available on-line from the
In a move that follows the success of the recent week-long workshop in
Stanford, we will have a second day to allow participants to complete
more sophisticated practical examples than are possible in the
- Function of an Internet Router
- Control plane
- Routing protocols
- Routing table
- Management and Command Line Interface (CLI)
- Address lookup
- Longest prefix match
- Classless Interdomain Routing (CIDR)
- Header update
- Packet buffer
- NetFPGA Router
- Gigabit Ethernet interfaces
- PCI host interface
- Field Programmable Gate Array (FPGA) Logic
- Random Access Memory (RAM)
- Kernel-space driver
- User-space applications
- System configuration
- Demonstration Topology
- Network of ten routers
- Ethernet switch
- Video server
- High Definition (HD) video client
- Routing tables
- Dynamic re-routing
- Integrated Circuit Design
- Look-Up Tables (LUTs)
- Configurable Logic Blocks (CLBs)
- Field Programmable Gate Arrays (FPGAs)
- Verilog Hardware Description Language (HDL)
- Registers, integers, arrays
- Synchronous storage elements
- Finite State Machines (FSMs)
- Hardware Debug
- Waveform monitor
- In-circuit logic emulation
- NetFPGA System Components
- Synthesis of tutorial router
- Java-based Graphical User Interface (GUI)
- Router architecture
- Buffer Size Experiment
- Experiment with TCP/IP flows
- Rule-of-thumb for the buffer size
- Round-trip propagation delay
- Capacity of bottleneck link
- Number of active flows
- Lower delay with smaller queues
- Enhanced Router
- Additional hardware
- Event capture module
- Rate limiter
- Delay module
- HD video transport
- Life of packet through the system
- Description of blocks
- Waveforms from logic analyser
- NetFPGA Projects
About the presenters
Andrew W. Moore is a Lecturer at the University
of Cambridge Computer Laboratory. He joined the permanent faculty of
Cambridge in 2007, prior to this he had been an EPSRC Roberts Fellow
at Queen Mary, University of London, an Intel Research Fellow in
Cambridge and foundation-researcher at the Cambridge Marconi research
laboratory. Throughout this time Andrew has focused upon network
characterisation and measurement, extensible monitoring for
application performance-analysis and large-scale Internet monitoring
and emulation. Interest in switch design has led to work in physical
line-coding for optical networks, and novel optical-switch
Andrew completed his Ph.D. with the Cambridge University Computer
Laboratory in 2001 and prior to that took a Masters degree and an
honours degree from Monash University in Melbourne. Australia. Alongside routine collaboration with AT&T, Endace, Intel, and
Microsoft, Andrew Moore has served as principal investigator on grants
from the UK Research Council (EPSRC) and a number of UK government
bodies. He is a chartered engineer with the IET and a member of the
IEEE, ACM and USENIX.
- David Miller
David Miller is a PhD student with the
Systems Research Group in the University of Cambridge Computer
Laboratory. He joined the laboratory after a long career in network
monitoring and FPGA design with Endace. David joined Endace as one of
its first employees after completing his Bachelor and Masters studies
with the University of Waikato, New Zealand.
A PhD student with Technical University in
Brno, Martin Zadnik is a hardware developer with the liberouter project
and has been involved in development of hardware-accelerated solutions
for the Czech academic networks since 2003.
Registration is now closed - the course is full.
- (Old) Registration details here
- Locally annotated google map here
A Bill of
Materials is available for the PC as used at the Cambridge and Eurosys 2008
tutorials. NB you don't need to get one for the tutorial - this is given
as useful information for those that want to know what kit to get to
make the NetFPGA go when you buy one yourself.