One-place FIFO internal structure

The dashed paths show a pair of optional bypasses, called bypass and pipeline, that may sometimes be installed.

Using either of them can provide speedup in terms of latency - but they may not help with timing closure because they can extend the critical path. In other words, their use can remove clock cycles but can also restrict clock frequency.

The output multiplexor is only needed if the dashed bypass wire is installed.

(BSV combination path details non-examinable.)

(Bluespec users' note: the default BSV FIFO is fully-registered and so introduces bubbles in both directions: it provides two variants with combinational paths which avoid bubbles in each direction respectively, called bypass and pipelined, but note that neither variant is fully-pipelined/fully-registered using the above definitions.)

The AND gates in the source and sink are typical in most application use styles: they only assert the enable if the ready signal is present, but if both the internal speedups are present we have, overall, a combinational loop. Many EDA tools do not support combinational loops. In this FIFO case, we have a parasitic RS latch. Careful analysis shows that the latch is never set and that there is an equivalent circuit that would provide the same behaviour without the loop. Automatic reworking of that nature is not embodied in typical logic synthesiser tools and so manual editing or a rewriting pass over the circuit from a special tool is needed.