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ACS P35-15/16 SoC D/M Slide Pack 4.1 (Bus/Network on Chip)
Verilog RTL: Modules, Protocols and Interfaces
Protocol and Interface
Transactional Handshaking
Transactional Handshaking in RTL (Synchronous Example)
Architecture: Bus and Device Structure
Basic Bus: One initiator (II).
Basic bus: Multiple Initiators (II).
Bridged Bus Structures.
Classes of On-Chip Protocol
Practical Bus Protocols on IP Blocks
BVCI Net-Level Protocol.
ARM AXI Bus: The Current Favourite
Supporting out-of-order operation using tags.
Network on Chip: Simple Ring.
Network on chip: Switch Fabrics.
Network on Chip: Higher Dimensions.
NoC Modelling
On-chip Busses Summary.