Using guarded atomic actions is an old and well-loved design paradigm.
The term `wiring' above is used in the sense of TLM models: binding initiators to target methods.
The intention was that a compiler can direct scheduling decisions to span various power/performance implementations for a given program.
But designs with an over-reliance on shared variables suffer RaW/WaR hazards when the schedule is altered.
»LINK: Small Examples~ »Toy BSV Compiler (DJG) First basic example: two rules: one increments, the other exits the simulation. This example looks very much like RTL: provides an easy entry for hardware engineers.
module mkTb1 (Empty); Reg#(int) x <- mkReg (23); rule countup (x < 30); int y = x + 1; // This is short for int y = x.read() + 1; x <= x + 1; // This is short for x.write(x.read() + 1); $display ("x = %0d, y = %0d", x, y); endrule rule done (x >= 30); $finish (0); endrule endmodule: mkTb1
Second example shows an interface declaration that is imported by both parties.
The example interface is for pipeline object that could have aribtrary delay. Sending process is blocked by implied handshaking wires (hence far less typing than Verilog) and in the future would allow the programmer or the compiler to retime the implementation of the pipe component.
module mkTb2 (Empty); Reg#(int) x <- mkReg ('h10); Pipe_ifc pipe <- mkPipe; rule fill; pipe.send (x); x <= x + 'h10; // This is short for x.write(x.read() + 'h10); endrule rule drain; let y = pipe.receive(); $display (" y = %0h", y); if (y > 'h80) $finish(0); endrule endmodule
But, imperative expression using a conceptual thread is also useful to have, so Bluespec has a behavioural sub-language compiler built in.
|34: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory.|