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Classical Imperative/Behavioural H/L Synthesis Summary

(Bachelor's Course End)

Logic synthesisers and HLS tools cannot synthesise into hardware the full set of constructs of a general programming language. There are inevitable problems with:

Generating good hardware requires global optimisation of the major resources (ALUs, Multipliers and Memory Ports) and hence automatic time/space folding.

New techniques are needed that note that wiring is a dominant power consumer in today's ASICs

The major EDA companies, Synopsys, Cadance and Mentor all heavily pushing C-to-Gates flows.

Altera (Intel) and Xilinx, the FPGA vendors, are now also promoting HLS tools.

IC industry is still highly skeptical!

Success of formal verification means abundance of formal specs for protocols and interfaces: automatic glue synthesis seems highly-feasible.

Further material is in the ACS P35 course: Synthesis from formal spec and so on: This is currently academic interest only ? Except for glue logic.

35: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory.