HOME       UP       PREV       FURTHER NOTES       NEXT (OVM/UVM)  

Automated Stimulus Generation (Directed-Random Verification)

Testbench automation: generate pseudo-random input under constraining assertions.

struct LLCHeader { v: int( bits:2); 0: int(bits 14); }
struct frame {
  llc: LLCHeader;
  destAddr: uint (bits:48);
  srcAddr: uint (bits:48);
  size: int (bits:32);  
  payload: list of byte;           
  keep payload.size() in [0..size];  }

The frame structure is accepted at an input port.

Testing will be inside envelope defined by 'keep' statements.

An heirarchy of specifications and constraints:

  extend frame { keep size == 0;  };

Commerical products: »Verisity's Specman Elite »www.open-vera.com

32: (C) 2012-18, DJ Greaves, University of Cambridge, Computer Laboratory.