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The idea of a ``stream cache'', where multimedia data is placed directly in the CPU cache, has been proposed. Possible operating system support methods have been suggested to provide a natural abstraction of the data stream to a user application. Finally an example implementation of an input stream cache has been demonstrated.

The use of an s-cache memory certainly adds complexity to the cache control hardware. However, the hardware complexity, as opposed to mental complexity, should be put in perspective; the only unusual component in our system is the cache controller itself (we use standard cache tag memory etc), which is implemented in a pair of Xilinx FPGAsgif and a couple of standard PALs (10ns 22V10s). The desire for a flexible mapping of i-, d- and s- cache regions would also add some complexity, but again only relatively small parts of the hardware would need changes.

This work continues; having designed the hardware, we believe that only through integration with the operating system and the provision of a straightforward user programming model can we expect applications to make use of it.

Mark Hayter, Derek McAuley et. al.