ECAD and Architecture Practical Classes
Principal lecturer: Prof Simon Moore
Taken by: Part IB CST
Term: Michaelmas
Format: In-person lectures
Prerequisites: Digital Electronics
timetable
Aims
The aims of this course are to enable students to apply the concepts learned in the Introduction to Computer Architecture course. There is further online training to learn the SystemVerilog hardware description language and RISC-V assembler. Online exercises are used to assess understanding.
Practical Classes
- Online learning of SystemVerilog including implementing multiple and divide for a RISC-V processor.
- Online learning of RISC-V assembler.
- Optional additional exercises including integrating a multiply/divide unit into a processor pipeline and more advanced SystemVerilog test.
Objectives
- Gain experience hardware and low-level software design.
- Learn how to debug hardware and software systems in simulation.
Recommended reading
Recommended reading
* Harris, S.L. and Harris, D.M. (2021).Digital Design and Computer Architecture, RISC-V Edition, Morgan Kaufmann. Note that the authors' earlier work is still of relevance - Digital design and computer architecture: from gates to processors - first edition in 2007 and second edition in 2012.