The purpose of the EPROMS test suite is to assist the people building the FPC3 board in fault diagnosis. The document describes version 2.2 of the test ROM. The FPC3 consists of two parts. The first is a processing unit based around an ARM RISC processor. The second section is a network unit consisting of the buffer memory and a DMA engine. Therefore there are two sets of tests in the whole test suite, each aiming to exercise one of these sections.
The basic processor section test examines the status of IOC, LEDs, serial line, ROM, DRAM. Given that the tests on this section pass, we can then assume that we basically have an functioning Archimedes and can start up the Wanda micro-kernel that will perform the second set of tests on the network section.
The second set of tests aims to exercise the network unit. It first tries to program and then re-program Xilinx, check data/irq lines from Xilinx to IOC, it then checks access to the SRAM, the state of the transmission Xilinx and also accessibility of the Podule bus (this is not really in the network section, but it is rather more convenient to do it here). It also sends cells to both the loopback FIFO and the transmission FIFO. This set of tests is started in auto-pilot mode, i.e. the all tests are performed with minimum verbosity and non-interactive. After that, we drop into interactive mode of the test suite, in which individual tests can be selected and executed in an interactive way. It also allows us to access to xi5tester, which is a beefed-up version of the xiromtester (this is what we called the network section test suite). xi5tester will be described in section 8.
Given that the hardware passes both of these tests, there should a high level of confidence that it has been constructed correctly.