This course is a prerequisite for VLSI Design (Part II).
Aims
This course aims to introduce electronic computer aided design (ECAD)
with a particular emphasis on the Verilog hardware description
language (HDL). The course differs from previous years since the
first four lectures have been replaced by an interactive tutor system
to teach Verilog (the Intelligent Verilog Compiler, or IVC).
The IVC will be used for the first two laboratory sessions and completed
as homework. The material the IVC covers is a prerequisite for the
remaining seven practical sessions. Material taught is prerequisite
for the remaining seven practical sessions.
Lectures
Introduction and motivation.
Current technology, technology trends, ECAD trends, challenges.
Logic modelling, simulation and synthesis.
Logic value and delay modelling. Discrete event and device
simulation. Automatic logic minimisation.
Chip, board and system testing.
Production testing, fault models, testability, fault coverage,
scan path testing.
Verilog systems design.
Practicalities of mapping Verilog and ARM assembler onto an FPGA
board. Signal processing of inputs. Tips and pitfalls when
generating larger modular designs.
The interactive Verilog compiler (IVC) teaches the synthesisable
subset of Verilog which is required to complete the laboratory
sessions.
Objectives
At the end of the course students should
be able to design, prototype and debug circuits using Verilog targeted
at programmable gate arrays (FPGA)
understand circuit simulation, synthesis and testing concepts
appreciate hardware/software codesign
Recommended books
The following books are recommended for reference only:
Smith, D.R. & Franzon, P.D. Verilog styles for synthesis of digital systems. Prentice Hall.
Thomas, D.E. & Moorby, P. (1995). The Verilog hardware description language. Kluwer Academic Publishers.
Sternheim, E., Singh, R., Madhaven, R. & Trivedi, Y. (1993). Digital design and synthesis with Verilog HDL. Automata.