COVISP-1
Compromising Emanations Signal Processor
User manual

Markus Kuhn

2008-03-11

Installation

To use COVISP-1, you need to perform the following steps:

Interactive serial-port control commands

Currently implemented are the following single-key commands for switching between different standard video modes, and for fine-tuning the pixel-clock frequency:

l list video modes
m current video mode parameters
d show distribution of input voltages
< > prev/next video mode
[ ] prev/next test signal
b B decrease/increase brightness (offset)
c C decrease/increase contrast (gain)
t T decrease/increase input center point (balance)
i invert polarity
r activate/deactivate rectification
I initial lookup-table mappings (brightness, gain, etc)
p toggle between ADC input port A and B
n N recall/store clock adjustment
q w clock adjustment
a s decrease/increase adjustment step size
h H decrease/increase htotal
v V decrease/increase vtotal
v V decrease/increase vtotal
← ↑ → ↓scroll image (sync-phase adjustment)

Selecting the video mode

Using “<” and “>”, the video timing can be switched between one of currently 31 different predefined modes listed by “l”, including most of the VESA standard modes. You can also type the 2-digit hexadecimal number of the video mode to select it directly.

If a non-standard mode is required, start from a similar standard mode and then try the keys “v”, “V” to adjust the exact number of lines per frame.

The following video modes are preconfigured:

  00:  640 x 480 @ 59.9 Hz | 31.5 kHz, 25.175 MHz |  800 x 525 | VESA SMT
  01:  640 x 480 @ 72.8 Hz | 37.9 kHz, 31.500 MHz |  832 x 520 | VESA DMT
  02:  640 x 480 @ 75.0 Hz | 37.5 kHz, 31.500 MHz |  840 x 500 | VESA DMT
  03:  640 x 480 @ 85.0 Hz | 43.3 kHz, 36.000 MHz |  832 x 509 | VESA DMT
  04:  800 x 600 @ 56.2 Hz | 35.2 kHz, 36.000 MHz | 1024 x 625 | VESA DMT
  05:  800 x 600 @ 60.3 Hz | 37.9 kHz, 40.000 MHz | 1056 x 628 | VESA DMT
  06:  800 x 600 @ 72.2 Hz | 48.1 kHz, 50.000 MHz | 1040 x 666 | VESA DMT
  07:  800 x 600 @ 75.0 Hz | 46.9 kHz, 49.500 MHz | 1056 x 625 | VESA DMT
  08:  800 x 600 @ 85.1 Hz | 53.7 kHz, 56.250 MHz | 1048 x 631 | VESA DMT
  09: 1024 x 768 @ 60.0 Hz | 48.4 kHz, 65.000 MHz | 1344 x 806 | VESA DMT
  0A: 1024 x 768 @ 70.1 Hz | 56.5 kHz, 75.000 MHz | 1328 x 806 | VESA DMT
  0B: 1024 x 768 @ 75.0 Hz | 60.0 kHz, 78.750 MHz | 1312 x 800 | VESA DMT
  0C: 1024 x 768 @ 85.0 Hz | 68.7 kHz, 94.500 MHz | 1376 x 808 | VESA DMT
  0D: 1152 x 864 @ 75.0 Hz | 67.5 kHz,108.000 MHz | 1600 x 900 | VESA DMT
  0E: 1280 x 960 @ 60.0 Hz | 60.0 kHz,108.000 MHz | 1800 x1000 | VESA DMT
  0F: 1280 x 960 @ 85.0 Hz | 85.9 kHz,148.500 MHz | 1728 x1011 | VESA DMT
  10: 1280 x1024 @ 60.0 Hz | 64.0 kHz,108.000 MHz | 1688 x1066 | VESA DMT
  11: 1280 x1024 @ 75.0 Hz | 80.0 kHz,135.000 MHz | 1688 x1066 | VESA DMT
  12: 1280 x1024 @ 85.0 Hz | 91.1 kHz,157.500 MHz | 1728 x1072 | VESA DMT
  13: 1600 x1200 @ 60.0 Hz | 75.0 kHz,162.000 MHz | 2160 x1250 | VESA DMT
  14: 1600 x1200 @ 65.0 Hz | 81.2 kHz,175.500 MHz | 2160 x1250 | VESA DMT
  15: 1600 x1200 @ 70.0 Hz | 87.5 kHz,189.000 MHz | 2160 x1250 | VESA DMT
  16: 1600 x1200 @ 75.0 Hz | 93.8 kHz,202.500 MHz | 2160 x1250 | VESA DMT
  17: 1600 x1200 @ 85.0 Hz |106.2 kHz,229.500 MHz | 2160 x1250 | VESA DMT
  18: 1792 x1344 @ 60.0 Hz | 83.6 kHz,204.750 MHz | 2448 x1394 | VESA DMT
  19: 1792 x1344 @ 75.0 Hz |106.3 kHz,261.000 MHz | 2456 x1417 | VESA DMT
  1A: 1856 x1392 @ 60.0 Hz | 86.3 kHz,218.250 MHz | 2528 x1439 | VESA DMT
  1B: 1856 x1392 @ 75.0 Hz |112.5 kHz,288.000 MHz | 2560 x1500 | VESA DMT
  1C: 1920 x1440 @ 60.0 Hz | 90.0 kHz,234.000 MHz | 2600 x1500 | VESA DMT
  1D: 1920 x1440 @ 75.0 Hz |112.5 kHz,297.000 MHz | 2640 x1500 | VESA DMT
  1E:  800 x 600 @ 75.6 Hz | 47.5 kHz, 50.110 MHz | 1056 x 628 | Toshiba 440CDX
  1F: 1024 x 768 @ 60.0 Hz | 47.5 kHz, 62.350 MHz | 1312 x 792 | Toshiba R100

Adjusting the clock frequency

The reconstruction of a video signal is extremely sensitive to clock-frequency drift. In the absence of externally supplied sync information, the clock frequency needs continuous manual adjustment to compensate temperature drift in the oscillators involved in both the target video system and the COVISP-1 board.

After the right video mode has been selected, use “q” and “w” to adjust the clock frequency precisely. The default step size is very fine, but can be raised 10× with “s” and lowered 10× with “a”.

If the clock frequency is still far from adjusted, the displayed image will lean to either the right or the left on the top. If it leans to the left, press “q”, if it leans to the right press “w”, until the image is exactly upright.

Once the image is upright, further fine tuning is needed to eliminate horizontal scrolling. If the image moves to the right, press “q”, if it moves to the left, press “w”.

Once you have stopped the horizontal and vertical motion by suitably fine-tining the pixel-clock frequency, you can use the cursor keys to center the image on the monitor. This phase adjustment is achieved by inserting or dropping pixels or lines each time one of the cursor keys is pressed. Pressing the cursor keys for too long may cause some monitors to believe that the video mode has changed and result in an adjustment.

Adjusting the image quality

When processing an intermediate-frequency (IF) output, active the rectification function with “r”, such that both positive and negative input voltages appear with increased brightness.

Then use “b” and “B” to adjust the display brightness of the 0 V input level and “c” and “C” to adjust the contrast (or input-to-output amplification gain in 1 dB steps). If preferred, use “i” to invert the image luminosity. “I” restores all these settings to their default.

On-board controls

The two right buttons, SW6 and SW7, adjust the pixel clock frequency. They work similar to the serial-port commands “q” and “w”, however their action accelerates the longer they are pressed. In a sense, the change in frequency achieved is exponential to the time the button is pressed down. This permits both very fine and very large corrections.

The two left buttons, SW4 and SW5 are general-purpose decrease/increase keys. Their meaning is defined by the binary number selected with switches 5–8 on the DIP-switch SW2. The following settings are currently supported:

SW2function of SW4/SW5
5678
0000disabled
0001switch pre-set video mode
0010change contrast/gain
0011change brightness
0100toggle rectification/inversion

(0 means open, 1 means closed)

The 2-digit 7-segment display shows the value of the parameter currently selected (or its eight least-significant bits).

The COVISP-1 firmware can be restarted by pressing the CPU reset button SW8.

The eight blue LEDs indicate the linear level of the rectified input signal. To avoid clipping at the selected ADC, the input voltage should be adjusted such that the rightmost LED remains dark most of the time.

Test signal

A simple test signal is available on the SMA connector labelled DAC A OUT. It can be fed back directly into the ADC A IN connector if no receiver is at hand, using the SMA cable provided with the development kit. This test signal consists of a 1 MHz square wave that performs a 180° phase jump every 800 periods. This will show up as a checkerboard pattern of 25x25 pixel squares in the 640x480@60Hz VESA SMT mode, if its pixel clock frequency has been lowered from 25.175 MHz to 25.000 MHz.

The drop-off in the signal level to the right of each vertical edge is due to the 1 MHz high-pass filter characteristic of the ADC input transformers.

Appendix A: Programming the board

If you have not received a board where the COVISP FPGA configuration and firmware has already been programmed into the 16 MByte onboard flash by Markus Kuhn, then this section describes how you can do this yourself. The same procedure applies if you want to upgrade your board to a newer COVISP version.

You first have to upload the covisp.sof configuration file into the FPGA, for example via the JTAG connector using the Altera USBBlaster and the programmer tool in Altera’s Quartus II development environment. If you do not already have a licence for the full Quartus II environment, you can also download their Windows stand-alone programmer (no licence key required) and install it on your PC. You also will have to install the appropriate JTAG cable driver.

However, this way you can only load COVISP into the FPGA's configuration SRAM, where it will only last while the board is powered up (or until the next FPGA reset).

To reprogram the board such that it can be operated as a stand-alone device, you have to upload this configuration into the onboard 16 MByte Flash memory. This is done using the NIOS II Flash Programmer, which comes with Altera's NIOS II development environment. You can invoke the flash programmer either from the NIOS II Eclipse GUI, or simply with the two command lines:

  sof2flash --offset=0x800000 --input=covisp.sof --output=covisp.flash
  nios2-flash-programmer --base=0x01000000 covisp.flash
The flash programmer requires that there is already a COVISP configuration in the FPGA's configuration SRAM when you run it, as it relies on an existing NIOS II design with JTAG debugging and flash interface being present in the FPGA. The --base=0x01000000 option tells the flash programmer, where the flash chip is found in the address space of the NIOS II processor and the --offset=0x800000 (= User1 configuration slot) option tells the flash programmer where in the flash chip the configuration should be stored. For details, consult the NIOS II Flash Programmer User Guide as well as the errata sheet for the board's data sheet.

More information

Contact: Dr Markus Kuhn
University of Cambridge
Computer Laboratory
15 JJ Thomson Avenue
Cambridge CB3 0FD
United Kingdom
Phone: +44 1223 3-34676
Fax: +44 1223 3-34678
Email: mgk25 @cl.cam.ac.uk
URL: http://www.cl.cam.ac.uk/~mgk25/