Compromising Emanations Signal Processor

Markus Kuhn


COVISP-1 is a device for visualising compromising video-signal emanations on a standard VGA display. It is connected to the intermediate-frequency output of a VHF/UHF wide-band tuner. It digitizes this signal, applies signal processing operations such as demodulation (rectification), offset and gain (brightness and contrast) adjustment, and blanking, adds sync pulses, and supplies the combined signal to a connected VGA monitor.

COVISP-1 does not include any frame buffer. It passes through the signal from the analog-to-digital to the digital-to-analog converter on a sample-by-sample basis. Therefore, the VGA output signal will have exactly the same frame-repetition rate as the input signal. The connected monitor must support the frequency range of the eavesdropping target. The timing parameters of the added sync pulses have to be manually adjusted to match those of the targeted display, in order to obtain a stable image.


COVISP-1 is implemented on the Altera DSP Development Kit, Stratix II Edition, which is based on the Altera EP2S60F1020C4 FPGA. The design incorporates an FPGA-implemented Altera NIOS-II 32-bit microcontroller with C firmware, for parameter adjustment and remote control, combined with a custom-designed FPGA circuit for real-time signal processing and sync-signal synthesis.

Technical data

Input signalIF tuner output, 20–500 MHz center frequency, <50 MHz bandwidth, AC coupled, peak level −1 to 1 V, 50 Ω
Output signal15-pin analog VGA connector, 75 Ω, 0 to 0.7 V
Sampling frequency120 MHz
Sampling resolution12 bit linear
Input resolution~0.5 mV quantization noise
Deflection frequency rangewell beyond the range of commonly used video modes, direct-digital synthesis via 32-bit 200 MHz counter
Deflection frequency resolution<10−8 relative frequency error
Sync pulse jitter< 10 ns
Preset video modes31
Signal gainAdjustable −70 to +70 dB
Signal DC offsettheoretically −5 V to +5 V, but clipped to 0–0.7 V VGA signal level
Processing optionsrectify, invert
Control system32-bit microcontroller with 128 kB RAM, no operating system
Remote controlRS-232, 57 600 kbit/s, 8 data bits, no parity
Local controls2-button adjustment of reference frequency
4-switch parameter selector
2-button parameter increment/decrement function
2x7-segment parameter display
CPU reset button
FPGA reboot button
Input level monitoring8 blue LEDs show 8-bin 1-bit linear histogram of rectified input
Test signal generator1 MHz square wave, 180° phase jump every 800 periods, results in checkerboard pattern in 640x480@60Hz VESA SMT mode with slightly reduced reference frequency

These parameters are preliminary and subject to change.

More information

Contact: Dr Markus Kuhn
University of Cambridge
Computer Laboratory
15 JJ Thomson Avenue
Cambridge CB3 0FD
United Kingdom
Phone: +44 1223 3-34676
Fax: +44 1223 3-34678
Email: mgk25