lowRISC tagged memory tutorial

• Future work

• Building the front-end server

• Modifying the contents of the RAMdisk

• Building the boot image from scratch

• Running tests on the Zedboard FPGA

• Simulating the Verilog (FPGA target) generated by Chisel

• Simulating the Verilog (ASIC target) generated by Chisel

• Using the C++ emulator generated by Chisel

• Running simulations using Spike

• Running simulations

• A guide to setting up the development environment

• Tagged memory tests

• Adding HW/SW support for the load and store tag instructions

• Tagged memory support

• Rocket core overview

• Rocket chip overview