⇡ lowRISC tagged memory tutorial

Future work

This is the first release of the lowRISC chip. It provides simple, but fully functional, support for tagged memory. In the following releases, we will provide tag support in the Spike simulator and add support for the L2 cache. We will also explore better ISA and core support for tags. Current work is also developing an untethered version of the SoC with the necessary peripherals.