Structured ASIC (masked gate array on smaller die) closes the gap between ASIC and FPGA.
The design is prototyped on FPGA and early customer shipments likewise. But FPGA vendor offers a turnkey cost reduction path.
For example, two implementations of the same design (Xilinx EasyPath in 2005):
| Device | NRE | Unit cost |
| Spartan-3 FPGA: | 0 | 12 USD |
| EasyPath E3S1500 | 75 KUSD | 1 USD |
Crossover at 6250 units.
Twelve year's later, no public pricing information is available, but the crossover point may be 100x greater. »Xilinx EasyPath 2017
Perhaps the cost-reduced part is just a faulty FPGA yield where the faults are known to be irrelevant for the customer's application?
| 11: (C) 2008-18, DJ Greaves, University of Cambridge, Computer Laboratory. |