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DRAM Internal Block Diagram

Single-bank, 4-bit wide, DRAM Chip Internal Block Diagram.

This DRAM has four data I/O pins and four internal planes, so no bank select bits. (Modern, larger capacity DRAMs have multiple such structures on their die and hence additional bank select inputs select which one is addressed.)

Row and column addresses are supplied successively (giving overall a four part address: bank, row, column and bit lane).

DRAM is not random access memory!

SRAM cell complexity versus DRAM cell

15: (C) 2008-18, DJ Greaves, University of Cambridge, Computer Laboratory.