HOME UP PREV NEXT (ASIC Design Flow Diagram)

Hardware Design Flow for an ASIC

ASIC: Application-Specific Integrated Circuit. The ASIC hardware design flow is divided by the Structural RTL level into:

Front End: specify, explore, design, capture, synthesise → Structural RTL
Back End: Structural RTL → place, route, mask making, fabrication.

There is a companion software design flow that must mesh perfectly with the hardware if the final product is to work first time.

This course will put as much emphasis on field-programmable parts (FPGAs) as on ASICs, since FPGA has now grown in importance.